Consolidated Positions List – Radiant Semiconductors

B.U Skills Experience Work Location Job code
DFT 2-10 years Bangalore & Noida DFT
Physical Design 2-10 years Bangalore & Noida PD
Synthesis/STA 2-12 years Bangalore STA
Analog Layout 2-10 years Bangalore Analog
RTL Design 2-10 years Bangalore & Noida RTL
VLSI Verification 3-15 years Bangalore & Noida Verification
Analog Circuit Design 2-10 years Bangalore Ckt.Des
FPGA 6-10 years Bangalore FPGA
AMS verification 3+ years Bangalore AMS
Emulation 4 – 9 years Bangalore EMU
System C 3+ years Bangalore SC

Radiant Semiconductors Current Job openings


Experience: 2-10 years
Location: Bangalore& Noida.
Job Description:
• Chip-level DFT insertion with sound knowledge of scan compression, MBIST & JTAG techniques
• Should have good post silicon DFT bringup and debug experience
• Hands on in multi-vendor DFT tools
• Create test plan for complex ASICs and drive the DFT implementation & verification
• Ability to guide people, multiplex many issues and set priorities

RTL Design

Experience: 2-10 years
Location: Bangalore& Noida.
Job Description:
• Hands on experience of coding in Verilog and VHDL.
• Understanding of Power Intent, Power estimation and checks.
• Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool.
• Specification writing.
• IP RTL development experience.
• Good knowledge of version control tools like Clearcase and Design sync.

ASIC Verification

Experience: 3-15 years
Location: Bangalore& Noida.
Job Description:
• Expert in UVM/OVM for Verification
• System verilog assertions
• Perl
• Functional + Code Coverage
• Verilog and VHDL
• Tools like Synopsys VCS,Cadence IUS or Mentor Questasim is Preferable
• Image Sensor knowledge is a plus
• Experience with SPI,AHB,AXI,PCIe,DDR is a plus

Physical Design (PD)

Experience: 2-10 years
Location: Bangalore& Noida.
Job Description:
• Thorough understanding and knowledge of the entire Back end flow rtl to gdsii
• Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus
• Should have expertise in Timing analysis and closure
• Should have Tcl and perl scripting skills
• Should have work experience in the latest technology nodes like 16nm/14nm
• Should be familiar with low-power design and their impact on Back end flow


Experience: 3-12 years
Location: Bangalore& Noida.
Job Description:
• Should have good timing concepts and able to close timing of Block/SoC independently
• Should have hands on experience in constraint generation
• Hands on experience in Logical synthesis like Design compiler/ Rc compiler
• Knowledge in Formal Verification. Comfortable with LEC/formality tools
• Should able to generate and implement functional Ecos
• Should have experience in Pre-layout and Post layout timing analysis in tools
• Should have experience in two industry standard tools like Primetime/ETS
• Hands on experience in crosstalk timing closure.
• Knowledge in Path based analysis, AOCV, DMSA is a plus.
• Knowledge in complete physical Design flow is a plus.

Analog Circuit Design

Experience: - 2-10 years
Location: -Bangalore
Job Description:
• Relevant experience in Analog & Mixed signal IO design.
• Able to define or interpret the requirements into circuit designs.
• Proven Analog Circuit design competency, like schematic generation and simulation on Cadence Tool sets. Worst case identification, top level simulation, Monte Carlo analysis, and simulation data analysis
• Post layout parasitic extraction and simulation, Top level verification, block level modeling, top level simulation
• Circuits include Linear Amplifiers, Drivers, Low-dropout regulators, Charge Pump- Regulators, Band gap and Buck/Boost converters, references, comparators.
• Experience on High speed serial/parallel data links (multi Gb/s), PHY circuits, transceivers, PLLs, Clock and Data Recovery circuits.
• Verify performance requirements using appropriate behavioural modeling, Spice simulation, and verification tools. Document designs and present reviews to peers.
• Knowledge on Physical Design methods and issues.


Experience: 6-10 years
Location: Bangalore
Job Description:
• Expertise in FPGA/SOPC Implementations
• End-to-End FPGA/System Development
• Expertise in Xilinx/Altera FPGA Implementation flow
• Logic Estimation
• FPGA Selection

RF layout

Experience: 3 -7 years
Location: Bangalore
Job Description:
• BE or MTech in Electronics/Electrical engineering with 3+ years of work experience.
• Candidate should be strong expertise in leading in one or more of the following IP Layouts.RF modules – LNA, TCA, Mixer, PA, VCO for WLAN, BT chip sets.
• Candidate should have a strong knowledge on devices and process/fabrication technology.
• Should have work experience in 65nm, 45nm, 28nm, 16/14nm etc
• Good understating of Deep Submicro issues and layout techniques.
• Expertise on matching, parasitic reduction, ESD, DFM etc.
• Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc.
• Cadence Virtuoso Layout editor (L/XL/GXL)
• Verification tools : Assura/PVS/Calibre/ Hercules
• Scripting Knowledge of perl/shell/skill are highly preferred

AMS verification

Experience: 3+ years
Location: -Bangalore
Job Description:
Understands System Verilog/Verilog well, even better if knows about real number modeling
• Analog circuits knowledge ( the more the better, however, basic understanding is the bare minimum requirement ) and spice syntax
• Basic understanding of verification, stimulus generation
• Pll , clocking and working knowledge of serial IOs is added advantage.
• Prior experience of analog and mixed signal validation would help
• Schematic building and simulation experience at minimum level is desirable. Preferably experienced in running XA tool.


Experience: 4 – 9 years
Location: -Bangalore
Job Description:
• Strong SOC RTL porting experience for Emulation device , specifically Synopsys Zebu platform
• Experience in Verification Testbench setup and execution using VCS
• Transactor integration experience in Emulation platform
• Experience with LPDDR1/2, PCIe, UART/I2C, JTAG, Lauterbach
• Good debug skills

System C

Experience: 6+ years
Location: -Bangalore
Job Description:
•Good SystemC/ TLM knowledge and programming skills, proof point given in previous projects. System level integration experience

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